The hierarchical or "segmented" bit line architecture was developed several years ago in order to increase the integration density of memory chips. This architecture allows for a reduced number of space-consuming sense amplifiers for a given number of memory cells, thus reducing chip size or increasing memory capacity for a given size chip.
FIG. 1 illustrates a conventional hierarchical bit line architecture of a semiconductor memory. In any given column C.sub.j of the memory cell array, a master bit line MBL.sub.j is selectively connected to one of a number of local bit lines, e.g. LBL.sub.i to LBL.sub.i+3. Each master bit line (MBL) is composed of a high conductivity metal and is located at a higher fabrication layer than the local bit lines (LBLs), i.e., it is vertically spaced from the local bit lines, where "vertical", as used herein, is the direction perpendicular to the major surface of the memory cell array. Each local bit line is directly connected to typically several hundred memory cells MC, each consisting of an access transistor 18 and a storage cell 16. The memory cells are disposed at a lower layer than the local bit lines. A word line (not shown) in each row such as R.sub.i, R.sub.i+1 connects to the gates of all transistors 18 in that row to selectively activate memory cells to be accessed. A control line 17 selectively connects an associated LBL to the MBL, such that in any given column, only one of the LBLs is connected to the MBL to access (read, write or refresh) memory cells coupled to that LBL.
The master bit line connects to one input of a sense amplifier for that column. In what is known as a folded hierarchical bit line architecture, each column includes master bit line pair consisting of a "true" master bit line and a "complementary" master bit line running in parallel to one another on the same side of the sense amplifier. The sense amplifier amplifies a differential voltage between the true and complementary MBLs to provide solid logic levels for readout and refresh operations. Both master bit lines of the pair are coupled to a plurality of associated local bit lines, as shown in FIG. 1 (i.e., the MBL shown may be either a true MBL or a complementary MBL). To access a memory cell coupled to the true MBL, both MBLs are precharged to a reference voltage, and then the word line connected to that cell is then raised to modify the voltage on the corresponding master bit line in accordance with the charge stored in that memory cell. The sense amplifier then amplifies the differential voltage between the MBL pair. An analogous procedure is performed to access cells coupled to the complementary MBL.
In an "open" hierarchical bit line configuration, operation is basically the same as the folded architecture, except that the true MBL runs on one side of the sense amplifier, and the complementary MBL extends on the opposite side.
In general, bit line capacitance is proportional to bit line length. As such, bit line length is limited by the maximum bit line capacitance that can be tolerated. The maximum capacitance is generally determined by the allowable sensing margin and the power dissipation. With the hierarchical bit line architecture, the master bit line capacitance per unit length is less than the local bit line capacitance per unit length, since the LBLs are directly coupled to the memory cells which significantly contribute to the LBL capacitance, whereas the MBLs are not directly coupled to the cells. Thus, for a given column length, the total capacitance can be significantly less than in a non-hierarchical layout (i.e., layouts with only one layer of bit lines, each extending the entire column length and directly coupled to the memory cells). Therefore, by using a hierarchical architecture, less space-consuming sense amplifiers are needed for a chip with a specific number of memory cells. That is, the architecture permits each sense amplifier to be used for more cells, coupled to the local bit lines and one long master bit line, thereby reducing the number of sense amplifiers per chip. A smaller chip size is thus possible, provided that the area allocated to the switches 14 and additional control circuitry does not exceed the area saved by reducing the number of sense amplifiers.
Recently, a high density DRAM referred to as a "diagonal bit line" (DBL) DRAM has been developed. With the DBL-type DRAM, the effective cell size is nearly 6F.sup.2, where F is the minimum feature size of the processing technology. An example of a diagonal bit line type DRAM is disclosed in an article entitled "FA 14.6: A 1 Gb DRAM for File Applications", by T. Sugibayashi et al., ISSC95/Session 14. That article discloses a DRAM using an open bit line architecture. The open bit line architecture, however, is more susceptible to noise-related problems than a folded bit line architecture.
FIG. 2 illustrates a folded bit line structure in which the folded bit lines run on top of one another, vertically spaced from each other by a dielectric layer, as opposed to running side by side in parallel at the same fabrication layer. The shown configuration is particularly suitable for use with cells smaller than 8F.sup.2. In order to facilitate access to the cells, a true bit line BL and a complementary bit line BL run on top of one another, alternately overlying and underlying each other. Memory cells MC in the different portions of the column C.sub.j are always coupled to the lower of the bit lines. At periodic regions designated as 13, the two bit lines undergo a "vertical twist", i.e. the bit lines cross over one another in the vertical direction. Each LBL segment S separating adjacent vertical twists is typically coupled to 2.sup.N memory cells, e.g., eight, sixteen, thirty-two, sixty-four, etc. It is noted that in FIG. 2, the bit lines are shown generally linear. For some diagonal cell designs, however, the bit lines run in a zigzag type pattern, changing horizontal direction each time that a vertical twist occurs.
An example of a memory cell array employing vertical twists for the bit lines is disclosed in co-pending U.S. patent application Ser. No. 08/884,853, attorney docket numbers 96E9190US and FI8960449, by John DeBrosse et al., filed Jun. 30, 1997, assigned to the assignee herein and incorporated herein by reference in its entirety (hereafter, the DeBrosse et al. application).
The hierarchical concept has also been applied to the word lines of semiconductor memories. A word line configuration designed to reduce memory cell access time (RC time constant of the word line) is referred to herein as a dual word line configuration.
FIG. 3 illustrates one example of a dual word line configuration, referred to as a "segmented" dual word line architecture. A master word line in the "ith" row R.sub.i is driven by a word line driver which is part of the row decoder of the memory. The master word line overlies associated local word lines LWL.sub.i1 -LWL.sub.iX in row R.sub.i on a different vertically-spaced layer, with a suitable dielectric layer separating the two layers. The local word lines are directly connected to the gates of the access transistors within memory cells MC in row R.sub.i. The master word line is composed of a low resistivity metal such as aluminum whereas the local word lines are typically composed of highly doped polysilicon with a silicide layer on top. A local word line driver 15 is coupled between each local word line and the master word line. Each local word line driver operates to drive the associated local word line to permit selective access of the cells coupled to that local word line.
FIG. 4 illustrates another type of dual word line configuration, referred to as a "stitched" architecture. The stitched architecture differs from the segmented architecture in that the local word line drivers are replaced by electrical via hole contacts or "stitches" 19 between the master word line MWL.sub.i and the local word lines LWL.sub.li to LWL.sub.xi. The local word lines may all be electrically connected as shown. With either the stitched or segmented architectures, the total resistance in the path to any given memory cell is substantially reduced. With lower word line resistance, the RC time constant associated with each word line is reduced, thereby speeding up memory cell access time. The segmented architecture has the additional advantage of reduced word line capacitance; however, a drawback to the segmented approach is the additional complexity and space required for the local word line drivers.